login - create an account - help
|
published by
the University of Minnesota
This course material covers a two and a half week introduction to VERILOG programming using FPGAs (Field Programmable Gate Arrays). It is an attempt to modernize the current digital lab course that is part of the advanced physics lab's electronics course segment.
Prior to these exercises, students have been exposed to basic analog and digital circuits, C programming and basic analog to digital and digital to analog converter concepts. The exercises cover the following topics: - Basic Verilog Syntax: modules, instantiation of modules, branching statements; - Pin assignment for wires and buses; - Combinational and Sequential Logic implementation. In the exercises, the students implement: - a simple 4 bit adder with a 7-Segment decimal display; - a radiation counter with a 7-Segment decimal display; - a simple Pulse Width Modulation (PWM) algorithm to control the brightness of an LED; - a Sigma-Delta PWM algorithm to make an Analog to Digital converter to play 8 and 16 bit music stored on flash memory modules. The hardware for the exercises consist of Digilent BASYS boards (with peripheral modules) which utilize a Xilinx Spartan 3-E FPGA. The Verilog programming is done with the (free) Xilix WebPack. The boards are programmed with the (free) Adept Software Suite.
ComPADRE is beta testing Citation Styles!
Record Link
<a href="https://www.compadre.org/portal/items/detail.cfm?ID=9347">University of Minnesota. Verilog Programming Exercises. Minneapolis: University of Minnesota.</a>
AIP Format
(University of Minnesota, Minneapolis), WWW Document, (http://spa-mxpweb.spa.umn.edu/resources/Verilog/Verilog.htm).
AJP/PRST-PER
Verilog Programming Exercises (University of Minnesota, Minneapolis), <http://spa-mxpweb.spa.umn.edu/resources/Verilog/Verilog.htm>.
APA Format
Verilog Programming Exercises. (n.d.). Retrieved May 10, 2024, from University of Minnesota: http://spa-mxpweb.spa.umn.edu/resources/Verilog/Verilog.htm
Chicago Format
University of Minnesota. Verilog Programming Exercises. Minneapolis: University of Minnesota. http://spa-mxpweb.spa.umn.edu/resources/Verilog/Verilog.htm (accessed 10 May 2024).
MLA Format
Verilog Programming Exercises. Minneapolis: University of Minnesota. 10 May 2024 <http://spa-mxpweb.spa.umn.edu/resources/Verilog/Verilog.htm>.
BibTeX Export Format
@misc{
Title = {Verilog Programming Exercises},
Publisher = {University of Minnesota},
Volume = {2024},
Number = {10 May 2024},
Year = {}
}
Refer Export Format
%T Verilog Programming Exercises %I University of Minnesota %C Minneapolis %U http://spa-mxpweb.spa.umn.edu/resources/Verilog/Verilog.htm %O text/html
EndNote Export Format
%0 Electronic Source %T Verilog Programming Exercises %I University of Minnesota %V 2024 %N 10 May 2024 %9 text/html %U http://spa-mxpweb.spa.umn.edu/resources/Verilog/Verilog.htm Disclaimer: ComPADRE offers citation styles as a guide only. We cannot offer interpretations about citations as this is an automated procedure. Please refer to the style manuals in the Citation Source Information area for clarifications.
Citation Source Information
The AIP Style presented is based on information from the AIP Style Manual. The APA Style presented is based on information from APA Style.org: Electronic References. The Chicago Style presented is based on information from Examples of Chicago-Style Documentation. The MLA Style presented is based on information from the MLA FAQ. |
ContributeSimilar Materials |
Save to my folders