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Verilog Programming Exercises
published by the University of Minnesota
This course material covers a two and a half week introduction to VERILOG programming using FPGAs (Field Programmable Gate Arrays).  It is an attempt to modernize the current digital lab course that is part of the advanced physics lab's electronics course segment.

Prior to these exercises, students have been exposed to basic analog and digital circuits, C programming and basic analog to digital and digital to analog converter concepts.  The exercises cover the following topics:
- Basic Verilog Syntax: modules, instantiation of modules, branching statements;
- Pin assignment for wires and buses;
- Combinational and Sequential Logic implementation.

In the exercises, the students implement:
- a simple 4 bit adder with a 7-Segment decimal display;
- a radiation counter with a 7-Segment decimal display;
- a simple Pulse Width Modulation (PWM) algorithm to control the brightness of an LED;
- a Sigma-Delta PWM algorithm to make an Analog to Digital converter to play 8 and 16 bit music stored on flash memory modules.

The hardware for the exercises consist of Digilent BASYS boards (with peripheral modules) which utilize a Xilinx Spartan 3-E FPGA.  The Verilog programming is done with the (free) Xilix WebPack.  The boards are programmed with the (free) Adept Software Suite.
http://mxp.physics.umn.edu/resources/Verilog/Verilog.htm
Subjects Levels Resource Types
Other Sciences
- Engineering
- Upper Undergraduate
- Instructional Material
= Course
= Curriculum
= Instructor Guide/Manual
= Laboratory
= Student Guide
= Tutorial
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Safety Warnings
Minimal Danger   No Safety Equipment Necessary  


Access Rights:
Free access
Restriction:
Has a copyright or other licensing restriction.
Keywords:
Digital Lab Exercises, FPGA
Record Creator:
Metadata instance created August 6, 2009 by Kurt Wick
Record Updated:
May 22, 2012 by Lyle Barbato
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AIP Format
(University of Minnesota, Minneapolis), WWW Document, (http://mxp.physics.umn.edu/resources/Verilog/Verilog.htm).
AJP/PRST-PER
Verilog Programming Exercises, (University of Minnesota, Minneapolis), <http://mxp.physics.umn.edu/resources/Verilog/Verilog.htm>.
APA Format
Verilog Programming Exercises. (n.d.). Retrieved July 20, 2018, from University of Minnesota: http://mxp.physics.umn.edu/resources/Verilog/Verilog.htm
Chicago Format
University of Minnesota. Verilog Programming Exercises. Minneapolis: University of Minnesota. http://mxp.physics.umn.edu/resources/Verilog/Verilog.htm (accessed 20 July 2018).
MLA Format
Verilog Programming Exercises. Minneapolis: University of Minnesota. 20 July 2018 <http://mxp.physics.umn.edu/resources/Verilog/Verilog.htm>.
BibTeX Export Format
@misc{ Title = {Verilog Programming Exercises}, Publisher = {University of Minnesota}, Volume = {2018}, Number = {20 July 2018}, Year = {} }
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%T Verilog Programming Exercises
%I University of Minnesota
%C Minneapolis
%U http://mxp.physics.umn.edu/resources/Verilog/Verilog.htm
%O text/html

EndNote Export Format

%0 Electronic Source
%T Verilog Programming Exercises
%I University of Minnesota
%V 2018
%N 20 July 2018
%9 text/html
%U http://mxp.physics.umn.edu/resources/Verilog/Verilog.htm


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